1. Field of the Invention
This invention relates to the field of voltage level translation circuits, and in particular, to the translation of Transistor-Transistor Logic (TTL) signals to Complementary Metal Oxide Silicon (CMOS) voltage levels.
2. Background Art
It is often desired to provide an interface between CMOS (integrated circuit) devices and TTL circuitry. In providing such an interface, it is necessary to convert the voltage levels of the TTL circuitry to levels which may be utilized in the CMOS circuitry.
Previous technology for the interface circuits involve comparator circuits with a reference voltage set for the mid-point of the TTL specification (e.g., 1.4-1.6 volts). Other prior art circuitry involved a CMOS inverter stage with transistor sizes selected to optimize the switching threshold near the TTL specification point. However, comparator circuits suffer from poor accuracy and are not suited for high-speed operation.
The CMOS inverter circuit is sensitive to process variations as it depends upon the relationship of transistor characteristics between P-channel and N-channel transistors. The two different devices (P-channel and N-channel) do not "track" or self-compensate in typical wafer fabrication processes. As a result, the switching threshold varies too much to ensure proper operation in the typical range of process variations and operating environments.
Another prior art TTL/CMOS translator is the static inverter type of translator. A static inverter-type of translator consists of 2 inverter stages of complementary transistors. The input TTL signal provides the gate voltage of the first drain coupled transistor pair. The first pair acts as a voltage divider and the output of this first pair is coupled to the gates of the second complementary pair. The output of the second stage is taken from the drain of the P-type transistor. Static inverter types of translators are not suitable for low standby current applications. These translators also suffer from VTN degradation induced by hot electron effects. In addition, such translators require very tight process control to achieve a stable VIL/VIH trip point.
One method of improving low standby current performance for prior art static inverter translators is to use longer channels and weaker transistors to reduce standby current and reduce hot electron effects on VTN degradation. However, this improves standby current and the process windows at the expense of speed.
Therefore, it is an object of the present invention to minimize the standby current and maintain the high-speed operation of a static inverter-type TTL/CMOS level translator.
It is another object of the present invention to suppress hot electron-induced VTN degradation in a TTL/CMOS translator.
It is yet another object of the present invention to provide a TTL/CMOS level translator with wide process window margins.